compile:
	vcs -full64 -sverilog -f  file.f -top  riscv_aes_tb -debug_acc+all -l complie.log
sim:
	./simv -l sim.log
debug:
	verdi -f file.f  -top  riscv_aes_tb  -ssf wave.fsdb &
recom:compile sim
all:compile sim debug

clean:
	rm -rf ./csrc *.daidir *.log simv* *.key *.vpd ./DvEfiles verdiLog novas*
